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Learn more about ECAD Model here.Electrical Characteristics
| Additional Feature | PAL BLOCKS INTERCONNECTED BY PIA; 8 PAL BLOCKS; BURIED MACROCELLS; 4 EXTERNAL CLOCKS |
| Clock Frequency-Max | 62.5 |
| In-System Programmable | NO |
| JESD-30 Code | S-PQCC-J68 |
| JESD-609 Code | e0 |
| JTAG BST | NO |
| Length | 24.2062 |
| Number of Dedicated Inputs | 4 |
| Number of I/O Lines | 48 |
| Number of Macro Cells | 96 |
| Number of Terminals | 68 |
| Operating Temperature-Max | 70 |
| Operating Temperature-Min | 0 |
| Organization | 4 DEDICATED INPUTS, 48 I/O |
| Output Function | MACROCELL |
| Package Body Material | PLASTIC/EPOXY |
| Package Code | QCCJ |
| Package Equivalence Code | LDCC68,1.0SQ |
| Package Shape | SQUARE |
| Package Style | CHIP CARRIER |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED |
| Power Supplies | 5 |
| Programmable Logic Type | EE PLD |
| Propagation Delay | 16 |
| Qualification Status | Not Qualified |
| Seated Height-Max | 4.57 |
| Sub Category | Programmable Logic Devices |
| Supply Voltage-Max | 5.25 |
| Supply Voltage-Min | 4.75 |
| Supply Voltage-Nom | 5 |
| Surface Mount | YES |
| Technology | CMOS |
| Temperature Grade | COMMERCIAL |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| Terminal Form | J BEND |
| Terminal Pitch | 1.27 |
| Terminal Position | QUAD |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Width | 24.2062 |