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Learn more about ECAD Model here.Electrical Characteristics
| Additional Feature | LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK |
| Clock Frequency-Max | 27.7 |
| In-System Programmable | NO |
| JESD-30 Code | S-CPGA-P100 |
| JESD-609 Code | e4 |
| JTAG BST | NO |
| Length | 33.3375 |
| Number of Dedicated Inputs | 19 |
| Number of I/O Lines | 64 |
| Number of Macro Cells | 128 |
| Number of Terminals | 100 |
| Operating Temperature-Max | 125 |
| Operating Temperature-Min | -55 |
| Organization | 19 DEDICATED INPUTS, 64 I/O |
| Output Function | MACROCELL |
| Package Body Material | CERAMIC, METAL-SEALED COFIRED |
| Package Code | WPGA |
| Package Equivalence Code | PGA100M,13X13 |
| Package Shape | SQUARE |
| Package Style | GRID ARRAY, WINDOW |
| Power Supplies | 5 |
| Programmable Logic Type | UV PLD |
| Propagation Delay | 59 |
| Qualification Status | Not Qualified |
| Screening Level | MIL-STD-883 |
| Seated Height-Max | 5.207 |
| Sub Category | Programmable Logic Devices |
| Supply Voltage-Max | 5.5 |
| Supply Voltage-Min | 4.5 |
| Supply Voltage-Nom | 4.5 |
| Surface Mount | NO |
| Technology | CMOS |
| Temperature Grade | MILITARY |
| Terminal Finish | GOLD |
| Terminal Form | PIN/PEG |
| Terminal Pitch | 2.54 |
| Terminal Position | PERPENDICULAR |
| Width | 33.3375 |