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74AUP1G74DC,125 | NEXPERIA

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NEXPERIA 74AUP1G74DC,125

D Flip-Flop, AUP/ULP/V Series, 1-Func,PositiveEdgeTriggered, 1-Bit, Complementary Output,CMOS,PDSO8


Ordering Info

In Stock: 45000 Delivery

MOQ: 3000

Package Quantity: 3000

HTS Code: 8542.39.00

ECCN: EAR99

COO: TH

Quantity Cost
3000-44999 $0.1986
45000+ $0.1853


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Electrical Characteristics

Family AUP/ULP/V
JESD-30 Code R-PDSO-G8
JESD-609 Code e4
Length 2.3
Logic IC Type D FLIP-FLOP
Moisture Sensitivity Level 1
Number of Bits 1
Number of Functions 1
Number of Terminals 8
Operating Temperature-Max 125
Operating Temperature-Min -40
Output Polarity COMPLEMENTARY
Package Body Material PLASTIC/EPOXY
Package Code VSSOP
Package Shape RECTANGULAR
Package Style SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Cel) 260
Propagation Delay (tpd) 23.3
Qualification Status Not Qualified
Seated Height-Max 1
Supply Voltage-Max (Vsup) 3.6
Supply Voltage-Min (Vsup) .8
Supply Voltage-Nom (Vsup) 1.2
Surface Mount YES
Technology CMOS
Temperature Grade AUTOMOTIVE
Terminal Finish Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal Form GULL WING
Terminal Pitch .5
Terminal Position DUAL
Time@Peak Reflow Temperature-Max (s) 40
Trigger Type POSITIVE EDGE
Width 2
fmax-Min 510