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74LV08N | NXP

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NXP 74LV08N

AND Gate, LV/LV-A/LVX/H Series,4-Func,2-Input,CMOS, PDIP14


Ordering Info

In Stock: 200

MOQ: 1

Package Quantity: 1

Quantity Cost
1 -

Electrical Characteristics

Family LV/LV-A/LVX/H
JESD-30 Code R-PDIP-T14
JESD-609 Code e4
Length 19.025
Load Capacitance (CL) 50
Logic IC Type AND GATE
Max I(ol) 0.006
Moisture Sensitivity Level NOT APPLICABLE
Number of Functions 4
Number of Inputs 2
Number of Terminals 14
Operating Temperature-Max 125
Operating Temperature-Min -40
Package Body Material PLASTIC/EPOXY
Package Code DIP
Package Equivalence Code DIP14,.3
Package Shape RECTANGULAR
Package Style IN-LINE
Peak Reflow Temperature (Cel) NOT SPECIFIED
Power Supplies 3.3
Prop Delay@Nom-Sup 19
Propagation Delay (tpd) 33
Qualification Status Not Qualified
Schmitt Trigger NO
Seated Height-Max 4.2
Sub Category Gates
Supply Voltage-Max (Vsup) 5.5
Supply Voltage-Min (Vsup) 1
Supply Voltage-Nom (Vsup) 3.3
Surface Mount NO
Technology CMOS
Temperature Grade AUTOMOTIVE
Terminal Finish NICKEL PALLADIUM GOLD
Terminal Form THROUGH-HOLE
Terminal Pitch 2.54
Terminal Position DUAL
Time@Peak Reflow Temperature-Max (s) NOT SPECIFIED
Width 7.62