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74LV74D,112 | NXP

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NXP 74LV74D,112

D Flip-Flop, LV/LV-A/LVX/H Series,2-Func,PositiveEdge Triggered, 1-Bit,ComplementaryOutput, CMOS,PDSO14


RoHS Compliant

Ordering Info

In Stock: 0

MOQ: 1140

Package Quantity: 1140

Quantity Cost
1140 -

Electrical Characteristics

Family LV/LV-A/LVX/H
JESD-30 Code R-PDSO-G14
JESD-609 Code e4
Length 8.65
Logic IC Type D FLIP-FLOP
Moisture Sensitivity Level 1
Number of Bits 1
Number of Functions 2
Number of Terminals 14
Operating Temperature-Max 125
Operating Temperature-Min -40
Output Polarity COMPLEMENTARY
Package Body Material PLASTIC/EPOXY
Package Code SOP
Package Shape RECTANGULAR
Package Style SMALL OUTLINE
Peak Reflow Temperature (Cel) 260
Propagation Delay (tpd) 33
Seated Height-Max 1.75
Supply Voltage-Max (Vsup) 5.5
Supply Voltage-Min (Vsup) 1
Supply Voltage-Nom (Vsup) 3.3
Surface Mount YES
Technology CMOS
Temperature Grade AUTOMOTIVE
Terminal Finish Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal Form GULL WING
Terminal Pitch 1.27
Terminal Position DUAL
Time@Peak Reflow Temperature-Max (s) 30
Trigger Type POSITIVE EDGE
Width 3.9
fmax-Min 48