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Learn more about ECAD Model here.Electrical Characteristics
| Additional Feature | BUILT IN DIAGNOSTICS; BYTE CONTROL |
| Family | S |
| JESD-30 Code | R-CDFP-F48 |
| JESD-609 Code | e0 |
| Load Capacitance (CL) | 50 |
| Logic IC Type | ERROR DETECTION AND CORRECTION CIRCUIT |
| Number of Bits | 16 |
| Number of Functions | 1 |
| Number of Terminals | 48 |
| Operating Temperature-Max | 125 |
| Operating Temperature-Min | -55 |
| Output Characteristics | 3-STATE |
| Package Body Material | CERAMIC, METAL-SEALED COFIRED |
| Package Code | DFP |
| Package Equivalence Code | FL48,.6 |
| Package Shape | RECTANGULAR |
| Package Style | FLATPACK |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED |
| Power Supplies | 5 |
| Power Supply Current-Max (ICC) | 400 |
| Propagation Delay (tpd) | 73 |
| Qualification Status | Not Qualified |
| Screening Level | 38535Q/M;38534H;883B |
| Seated Height-Max | 2.4892 |
| Sub Category | Arithmetic Circuits |
| Supply Voltage-Max (Vsup) | 5.5 |
| Supply Voltage-Min (Vsup) | 4.5 |
| Supply Voltage-Nom (Vsup) | 5 |
| Surface Mount | YES |
| Technology | BIPOLAR |
| Temperature Grade | MILITARY |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| Terminal Form | FLAT |
| Terminal Pitch | 1.27 |
| Terminal Position | DUAL |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Width | 16.256 |