ASIX AX11015LI

Product Info

The AX11015, Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY, is a System-on-Chip (SoC) solution which offers a high performance embedded micro controller and rich communication peripherals for wide varieties of application which need access to the LAN or Internet. With built-in network protocol stack, the AX11015 provides very cost effective networking solution to enable simple, easy and low cost Internet connection capability for many applications such as consumer electronics, networked home appliances, industrial equipments, security systems, remote data collection equipments, remote control, remote monitoring and remote management. In addition to stand-alone application, the AX11015, with popular TCP/IP protocol suite on-chip and built-in local bus host interface, I¦C bus, or SPI bus, can be used as network co-processor to offload TCP/IP protocol processing loading from system CPU in an embedded system

Feature:

MCU

8-bit pipelined RISC, single cycle per instruction with maximum operating frequency of 100MHz (100 MIPS)

100% software compatible with standard 8051/80390

4 GPIO ports of 8 bits each

2 external interrupt sources with 2 priority levels

Supports power management unit, programmable watchdog timer and 3 16-bit timer/counters

Debug port for connecting to In-Circuit Emulation (ICE) adaptor

5 channels of Programmable Counter Array (PCA)

On-chip Program and Data Memory

Embeds 512KB Flash memory and 16KB SRAM for program code mirroring. The external program memory can grow up to 2MB without bank select

Supports initial Flash memory programming via UART or ICE adaptor, the so-called In System Programming (ISP)

Supports reprogrammable boot code and In Application Programming (IAP) to update run-time firmware or boot code through Ethernet or UART (US Patent Approval)

Supports boot loader to shadow program code on to internal 16KB SRAM and external SRAM for high performance applications

Embeds 32KB SRAM for data memory, expandable up to 2MB via external SRAM without bank select

Buffer Management

Innovative shared memory architecture to allow external program and data memory to share the same SRAM memory chip with flexible memory space allocation

Embeds DMA engine and memory arbiter. Support 5 DMA channels for high performance data movement needed for network protocol stack processing

On-chip 10/100M Fast Ethernet MAC and PHY

Integrates IEEE 802.3 10BASE-T/100BASE-TX compatible Fast Ethernet MAC and PHY with dedicated 12KB SRAM for Ethernet packet buffering. Support full-duplex and half-duplex operations. Provide optional MII interface (for HomePNA and HomePlug)

Supports twisted pair crossover detection and auto-correction (Auto-MDIX)

Supports wakeup via Link-up, Magic packet, Wakeup frame or external input pin

TCP/IP

Builds in TCP/IP accelerator in hardware to improve network transfer throughput. Support IP/TCP/UDP/ICMP/IGMP checksum and ARP in hardware

Supports TCP, UDP, ICMP, IPv4, DHCP, BOOTP, ARP, DNS, SMTP, SNTP, uPNP, PPPoE and HTTP in software

Communication Interface

3 UART interface (with 1 supporting 921.6Kbps and Modem control)

I¦C interface (master and slave mode)

Local bus host interface (master or slave mode)

SPI/Micro wire interface (3 masters or 1 slave mode)

1-Wire controller interface (master mode)

10/100 Ethernet PHY interface

Supports network boot over Ethernet using BOOTP and TFTP

Integrates on-chip 3.3V to 1.8V voltage regulator and require single power supply of 3.3V only

Integrates on-chip oscillator and PLL. Require only one 25MHz crystal to operate

Integrates on-chip power-on reset circuit

128-pin LQFP RoHS package

Operati