AX88178A can be used in any embedded system with a USB host microcontroller requiring a twisted pair physical network connection. Featuring a USB interface (compliant with USB specification V2.0 and V1.1) to communicate with a USB Host Controller, the AX88178A also integrates on-chip Gigabit Ethernet MAC and PHY (IEEE802.3, IEEE802.3u and IEEE802.3ab compatible). Additionally, the AX88178A needs only a single 25MHz crystal to drive both the USB and Ethernet PHYs.
The AX88178A offers a wide array of features including IPv4/IPv6 checksum offload engine, crossover detection and auto-correction, TCP large send offload and IEEE802.3az EEE (Energy Efficient Ethernet). The EEE defines a mechanism that allows the AX88178A to enter a low power idle state to reduce power and to achieve a more energy efficient Ethernet. It supports dynamic cable length detection and dynamic power adjustment Green Ethernet in Gigabit mode. The AX88178A also offers multiple power management Wake-on-LAN features, including Magic Packet, Microsoft Wakeup Frame and Link Status Change that allows systems to enter a low power state and wake on desired network traffic.
Features:
Single chip USB 2.0 to 10/100/1000M Gigabit Ethernet controller with Energy Efficient Ethernet (EEE) base on digital signal processing (DSP) technology with low dissipation USB Device Controller Integrates on-chip USB 2.0 PHY and controller compliant to USB Spec 2.0 and 1.1 Supports USB High/Full Speed modes with Bus-power or Self-power device auto-detect capability High performance packet transfer rate over USB bus using proprietary burst transfer mechanism (US Patent Approval) Gigabit Ethernet Controller Supports IEEE 802.3az (Energy Efficient Ethernet) IEEE 802.3, 802.3u and 802.3ab compatible Integrates 10/100/1000Mbps Gigabit Ethernet MAC/PHY Supports dynamic cable length detection and dynamic power adjustment Green Ethernet (Gigabit mode only) Supports parallel detection and automatic polarity correction Supports crossover detection and auto- correction Supports IPv4/IPv6 packet Checksum Offload Engine (COE) to reduce CPU loading, including IPv4 IP/TCP/UDP/ICMP/IGMP & IPv6 TCP/UDP/ICMPv6 checksum check & generation Supports TCP Large Send Offload V1 Supports full duplex operation with IEEE 802.3x flow control and half duplex operation with back-pressure flow control Supports IEEE 802.1P Layer 2 Priority Encoding and Decoding Supports IEEE 802.1Q VLAN tagging and 2 VLAN ID filtering; received VLAN Tag (4 bytes) can be stripped off or preserved Supports Jumbo frame up to 4KB PHY loop-back diagnostic capability Support Wake-on-LAN Function Supports suspend mode and remote wakeup via link-change, Magic Packet, Microsoft Wakeup Frame and external wakeup pin Supports Bonjour wake-on-demand Advanced Power Management Features Supports power management offload (ARP & NS) Supports dynamic power management to reduce power dissipation during idle or light traffic Supports AutoDetach power saving-Soft-disconnected from USB host when Ethernet cable is unplugged Supports advanced link down power saving when Ethernet cable is unplugged Supports optional serial EEPROM (93c56/66) for storing USB Descriptors, Node-ID, etc. Supports embedded eFuse (64-byte) to store USB Device Descriptors, Node-ID, etc to save external EEPROM Supports automatic loading of USB Device Descriptors, Node-ID, etc. from embedded eFuse or external EEPROM after power-on initialization Single 25MHz clock input from either crystal or oscillator source Integrates on-chip power-on reset circuit Integrates pipelined RISC (System on a Chip, SoC) for handling protocol and control functions 68-pin
