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Feel trapped following the over provisioned High Cost Memory Standards Road Map? Etron developed a new evolutionary memory architecture: A RPC-DRAM®. This innovative patented architecture is an enabling solution to the new emerging markets of IOT, AR/VR and AI. It uses less than half the pins of a standard DDR3 memory yet still delivers low power, high speed and uses DDR3/LPDDR3 signaling.
With fewer signal pins and a smaller footprint the overall system cost can be significantly reduced. Controller cost is less, signal layout less complex, overall footprint is reduced, and advanced process nodes aren't required to meet the application requirements.
- Reduced Pin Count Architecture
- Less than half the pin count of a standard DRAM
- Only 22/24 Active signals
- Supports overlapped row/column operations
- Random addressing at full bandwidth
- High Performance
- Bandwidth > DDR3 with < ½ the signals
- Low Power: No DLL, Deep Power Down Mode
- DDR3/LPDDR3 Signaling
- Up to DDR2400 signaling speed
- X16 device: 4.8 GBytes /sec @ DDR2400
- Low Cost Package Options
- First DRAM offered in WLCSP (lowest cost pkg)
- DDR3 96 ball PCB footprint is 10X larger than RPC
- Stacked Die MCPs
- X32 DDP in same package as DDR3 X16 package
- Scalable Density and Configurations
- 64Mb to 8Gb
- X16, X32, X64
- Cost Effective Miniaturization
- Smallest Package size available WLCSP
- Same BW as DDR3 with <10% the footprint
- Controller size and complexity greatly reduced
- Overall PCB size and complexity reduced