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GAL20V8A-15LNC | NATIONAL SEMICONDUCTOR

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NATIONAL SEMICONDUCTOR GAL20V8A-15LNC

EE PLD, 15ns, PDIP24


Ordering Info

In Stock: 26

MOQ: 1

Package Quantity: 1

Quantity Cost
1 -

Electrical Characteristics

Additional Feature 8 MACROCELLS; SHARED INPUT/CLOCK; REGISTER PRELOAD
Architecture PAL-TYPE
Clock Frequency-Max 45.5
JESD-30 Code R-PDIP-T24
JESD-609 Code e0
Length 31.915
Number of Dedicated Inputs 12
Number of I/O Lines 8
Number of Inputs 20
Number of Outputs 8
Number of Product Terms 64
Number of Terminals 24
Operating Temperature-Max 75
Operating Temperature-Min 0
Organization 12 DEDICATED INPUTS, 8 I/O
Output Function MACROCELL
Package Body Material PLASTIC/EPOXY
Package Code DIP
Package Equivalence Code DIP24,.3
Package Shape RECTANGULAR
Package Style IN-LINE
Peak Reflow Temperature (Cel) NOT SPECIFIED
Power Supplies 5
Programmable Logic Type EE PLD
Propagation Delay 15
Qualification Status Not Qualified
Seated Height-Max 5.08
Sub Category Programmable Logic Devices
Supply Voltage-Max 5.25
Supply Voltage-Min 4.75
Supply Voltage-Nom 5
Surface Mount NO
Technology CMOS
Temperature Grade COMMERCIAL EXTENDED
Terminal Finish Tin/Lead (Sn/Pb)
Terminal Form THROUGH-HOLE
Terminal Pitch 2.54
Terminal Position DUAL
Time@Peak Reflow Temperature-Max (s) NOT SPECIFIED
Width 7.62