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Electrical Characteristics
| Additional Feature | INVERTING, NON INVERTING AND NAND GATES ACTING AS DELAY ELEMENTS |
| Family | LS |
| JESD-30 Code | R-PDIP-T16 |
| JESD-609 Code | e4 |
| Length | 19.304 |
| Logic IC Type | ACTIVE DELAY LINE |
| Moisture Sensitivity Level | NOT APPLICABLE |
| Number of Functions | 1 |
| Number of Taps/Steps | 0 |
| Number of Terminals | 16 |
| Operating Temperature-Max | 70 |
| Operating Temperature-Min | 0 |
| Output Polarity | TRUE |
| Package Body Material | PLASTIC/EPOXY |
| Package Code | DIP |
| Package Equivalence Code | DIP16,.3 |
| Package Shape | RECTANGULAR |
| Package Style | IN-LINE |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED |
| Power Supplies | 5 |
| Power Supply Current-Max (ICC) | 20 |
| Programmable Delay Line | NO |
| Prop Delay@Nom-Sup | 48 |
| Qualification Status | Not Qualified |
| Seated Height-Max | 5.08 |
| Sub Category | Delay Lines |
| Supply Voltage-Max (Vsup) | 5.25 |
| Supply Voltage-Min (Vsup) | 4.75 |
| Supply Voltage-Nom (Vsup) | 5 |
| Surface Mount | NO |
| Technology | TTL |
| Temperature Grade | COMMERCIAL |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Terminal Form | THROUGH-HOLE |
| Terminal Pitch | 2.54 |
| Terminal Position | DUAL |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Total Delay-Nom (td) | 95 |
| Width | 7.62 |