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Learn more about ECAD Model here.Electrical Characteristics
| Clock Frequency-Max | 250 |
| Combinatorial Delay of a CLB-Max | 0.8 |
| JESD-30 Code | S-PBGA-B680 |
| JESD-609 Code | e0 |
| Length | 40 |
| Moisture Sensitivity Level | 3 |
| Number of CLBs | 4704 |
| Number of Equivalent Gates | 888439 |
| Number of Inputs | 512 |
| Number of Logic Cells | 21168 |
| Number of Outputs | 512 |
| Number of Terminals | 680 |
| Operating Temperature-Max | 85 |
| Operating Temperature-Min | 0 |
| Organization | 4704 CLBS, 888439 GATES |
| Package Body Material | PLASTIC/EPOXY |
| Package Code | LBGA |
| Package Equivalence Code | BGA680,39X39,40 |
| Package Shape | SQUARE |
| Package Style | GRID ARRAY, LOW PROFILE |
| Peak Reflow Temperature (Cel) | 225 |
| Power Supplies | 1.2/3.6,2.5 |
| Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY |
| Qualification Status | Not Qualified |
| Seated Height-Max | 1.7 |
| Sub Category | Field Programmable Gate Arrays |
| Supply Voltage-Max | 2.625 |
| Supply Voltage-Min | 2.375 |
| Supply Voltage-Nom | 2.5 |
| Surface Mount | YES |
| Technology | CMOS |
| Temperature Grade | OTHER |
| Terminal Finish | Tin/Lead (Sn63Pb37) |
| Terminal Form | BALL |
| Terminal Pitch | 1 |
| Terminal Position | BOTTOM |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Width | 40 |