ASIX AX88782LF

Product Info

The AX88782 is a single-chip 2-port 10/100M Ethernet Switch controllers featuring a 3-port switching fabric with QoS priority management, three 10/100M MACs, two 10/100M PHYs, and 8/16-bit Non-PCI host interface. The AX88782 supports checksum offload engine and burst-mode access making it easy to provide a high performance 2-port Ethernet connectivity solution for any embedded MCU. The built-in switching fabric in the AX88782 supports non-blocking wire-speed forwarding and offers an advanced switch feature set that includes tag/port-based VLAN, spanning tree, rate control, port security, port mirroring, IGMP snooping, MIB counters and four priority queues for QoS functions including Port-Based, 802.1p VLAN, IPv4 TOS and IPv6 COS to prioritize voice, video, audio and data traffic delivery.

The AX88782 have integrated a voltage regulator and provide support for programmable I/O voltage options of 3.3V/2.5V/1.8V to enable a highly optimized system design. As semiconductor designs migrate to advanced process geometries like 90nm, 65nm, 45nm and beyond, many of today's higher performance ASICs, SoCs and FPGAs require lower I/O voltages.

The AX88782 combine the benefits of high integration and small form factor making them ideal single-chip solutions for designing high performance, QoS-aware and cost effective 2-port Ethernet functions for embedded system applications such as VoIP phone/ATA adapters, surveillance IP cameras, next-generation IP-STB/IPTV, industrial controller/network sensors, port redundancy/port monitoring and Single Board Computers (SBC)

Features:

High Performance Non-PCI Interface

Configurable 8/16-bit SRAM-like host interface (US Patent Approval), easily interfaces with most common embedded MCUs

Supports PPPoE/IPv4 IP/TCP/UDP/ICMP/ IGMP checksum offload to relieve CPU loading

Supports burst-mode access, minimizing CPU overhead

Fast Ethernet MAC/PHY

IEEE 802.3 10Base-T/100Base-TX compatible

Supports full-duplex operation with IEEE 802.3x flow control and half duplex with backpressure

10/100M PHY supports twisted pair crossover detection and auto-correction (HP Auto-MDIX)

Supports Wake-on-LAN by Microsoft Wakeup Frame, Magic Packet and link status change detection

Switching Fabric

Performs non-blocking wire-speed forwarding and filtering

Embeds 32KB SRAM for packet buffering

Supports broadcast storm filtering

Supports per queue and per port ingress and egress programmable rate limit control

Integrates two-way Address-Lookup engine and table for 1K MAC addresses

Supports Routing Table/IGMP/VLAN Table access through CPU read/write operation

Supports 802.1D Spanning Tree Protocol and 802.1w Rapid Spanning Tree Protocol

QoS

Supports Quality-of-Service for port-based, 802.1p VLAN and IPv4 TOS/IPv6 COS packets with four priority queues

Supports RFC2475 DiffServ-based

VLAN

Supports up to 3 VLAN groups for port-based VLAN and 16 VLAN entries for 802.1Q tag-based VLAN function

Supports Double tagging 802.1Q-in-802.1Q function for WAN access

Security

Supports ingress port security mode, incoming packets with unknown source MAC address could be dropped

Supports eight Security MAC Registrations

Supports 802.1X port-based Authorization

Multicast

Supports GMRP/GVRP/GARP packet snooping

Supports IPv4 IGMP and IPv6 ICMP/MLD (Multicast Listener Discovery) Snooping

Supports up to 1K Multicast Group (shared with L2 MAC table)

Supports eight IGMP Multicast IP address snooping

Monitoring

Supports RMON group 1,2,3,9 counter (RFC1213)

Supports Ethernet-like MIB counter (RFC 1643)

Supports Bridge MIB counter (RFC 1493)

Egress/Ingress Port Mirroring